(1) Field of the Invention
The present invention relates to solid-state imaging devices, such as a CCD image sensor, and driving methods thereof, and particularly to a technique for isolating a photodiode.
(2) Description of the Prior Art
Recent solid-state imaging devices have achieved high-pixel density of 10 million pixels or more, which allows the users to record a still picture as clear as a picture taken on silver film, and a moving picture. Along with the introduction of the devices having the high-pixel density, a pitch of a unit pixel size of a solid-state imaging device becomes smaller than 2 μm, and the unit pixel size continues to be miniaturized. With reference to an interline-transfer solid-state imaging device (ITCCD) as an example, a structure of a conventional solid-state imaging device and a driving method thereof (Patent Reference: Japan Unexamined Patent Application Publication No. 2005-93915) shall be described hereinafter.
FIG. 1 is a schematic block diagram of a conventional ITCCD.
The ITCCD includes: a photodiode 532 provided two-dimensionally on a semiconductor substrate (not shown); a column CCD 533 for transferring in a column direction signal charge accumulated in the photodiode 532; a row CCD 535 for transferring in a row direction the signal charge transferred by the column CCD 533; and an output unit 536 detecting, and outputting the signal charge transferred by the row CCD 535.
FIG. 2 is a cross-sectional view of the conventional ITCCD (a cross-sectional view taken from the line A-A′ of FIG. 1).
A p-type well region 538 is formed in an n-type semiconductor substrate 537. In the p-type well region 538, a highly-concentrated n-type semiconductor region (signal charge accumulation region) 539 and a highly-concentrated p-type semiconductor region (positive charge accumulation region) 540, composing the photodiode 532, is formed. On the n-type semiconductor region 539 is formed.
Further, in the p-type well region 538, an n-type channel region (charge transfer region) 541 composing the column CCD 533 is formed. The p-type semiconductor region 542 is formed under the channel region 541. On a side of the channel region 541, a p-type channel stop region 543 is formed.
A transfer electrode 546, serving as a read-out electrode and a transfer electrode, is formed above the semiconductor substrate 537 via an insulation film 545. Over the transfer electrode 546, a photo-shield film 548 is formed via an interlayer insulating film 547.
Here, the transfer electrode 546 includes: a transfer electrode serving as a read-out electrode for reading out the signal charge from the photodiode 532 to the column CCD 533 (also referred to as “read-out gate”, hereinafter); and a transfer electrode not serving as a read-out electrode, that is, only for transferring the signal charge in a column direction (also referred to as “non read-out gate”, hereinafter).
FIG. 3 shows a driving pulse controlling unit driving the column CCD 533. FIG. 4 shows a wave form of a voltage pulse provided from the driving pulse controlling unit (φV pulse). It is noted that FIG. 4 shows a wave form of a voltage pulse applied to the read-out gate. The wave form of the voltage pulse applied to the non read-out gate is a wave form of which the voltage pulse illustrated in FIG. 4 has no HIGH level voltage VH.
The driving pulse controlling unit generates a voltage pulse (column transfer pulse) out of the incoming HIGH level voltage VH, a MIDDLE level voltage VM, and a LOW level voltage VL.
In the ITCCD structured above: the HIGH level voltage VH is applied to the read-out gate at a signal charge read time T1; and the signal charge accumulated in the photodiode 532 is read out to the column CCD 533, before the voltage pulse becomes the MIDDLE level voltage VM. Then, as shown in a voltage change at T2, voltage changes of the MIDDLE level voltage VM and the LOW level voltage VL are applied to the read-out gate and the non read-out gate, and thus, the signal charge is transferred in a column direction.
When the MIDDLE level voltage VM is applied to either the read-out gate or the non read-out gate, the underneath of the gate is in a state of accumulating the signal charge, so that the signal charge (electron) is accumulated. Meanwhile, when the LOW level voltage VL is applied, the underneath of the gate is in a barrier state. Hence, the signal charge is displaced. Several read-out gates and several non read-out gates form a group. Either the MIDDLE level voltage VM or the LOW level voltage VL is applied to each of the read-out gates or non read-out gates, so that signal charge in each of the photodiodes is transferred in a column direction without mixing.
While the HIGH level voltage VH is not applied to the read-out gate, photo-electrically converted electrons are accumulated in the photodiode 532 until the next HIGH level voltage VH is applied. Here, a large amount of incident light causes the photodiode 532 to be saturated with the signal charge until the next HIGH level voltage VH is applied, so that the signal charge exudes to a neighboring column CCD 553, and causes blooming. In order to avoid this, a typical technique is to extract excessive signal charge to an overflow drain (not shown) in a deep part of the substrate.